FIG. 14 is a diagram illustrating the structure of a conventional PLL equipped with a variable frequency divider has pulse-swallow architecture.
As shown in FIG. 14, the PLL comprises an amplifier 201 for amplifying the output (whose frequency ftcxo is 14.4 MHz) of an externally mounted temperature-compensated crystal oscillator (TCXO) 200; a reference-frequency dividing circuit 202 for frequency-dividing the output of the amplifier 201; a phase comparator 203 for sensing the phase difference between a reference signal (frequency f≈400 KHz), which is the result of frequency division by the reference-frequency dividing circuit 202, and a frequency-divided clock; a charge pump 204 for charging a capacitance (not shown) when the phase comparator 203 is outputting an UP signal in accordance with the result of the phase comparison and for discharging the charge, which has accumulated in the capacitance, when the phase comparator 203 is outputting a DOWN signal in accordance with the result of the phase comparison; a low-pass filter (loop filter) LPF 205 for smoothing the terminal voltage of the capacitance charged/discharged by the charge pump 204; a voltage-controlled oscillator (VCO) 206, to which the output voltage of the LPF 205 is input as a control voltage, for oscillating at a frequency conforming to the control voltage and outputting a signal having this frequency; a divide-by-P or divide-by-(P+1) frequency dividing circuit (referred to also as a “prescaler”) 207 composed by ECL (emitter-coupled logic) circuits for frequency-dividing the output of the voltage-controlled oscillator 206 by P or (P+1); and an A counter 209 and B counter 210 for counting the output of the prescaler 207. The phase comparator 203 compares the phase of an (A×P+B)-divided signal, which is output from a control circuit 213, and the phase of the reference signal.
An MC (modulus control) signal supplied to the prescaler 207 from the B counter 210 is a control signal for changing the frequency-dividing factor of the P, (P+1) frequency dividing prescaler 207. The prescaler 207 functions as a divide-by-P prescaler when the signal MC is at HIGH level and as a divide-by-(P+1) prescaler when the signal MC is at LOW level.
A modulus-control prescaler circuit according to the prior art will be described with reference to FIG. 15, which is a diagram illustrating the prescaler 207 and counters 209 and 210 extracted from the PLL circuit shown in FIG. 14.
As shown in FIG. 15, the prescaler 207 includes D-type flip-flops 22 to 25 each of which has its data output terminal connected to the data input terminal of the D-type flip-flop of the next stage and each of which has a clock terminal to which an output signal of the voltage-controlled oscillator (referred to simply as a “VCO”) 206 is supplied to thereby construct a 4-stage shift register; an OR gate 21 having a first input terminal connected to an inverting output terminal QB of the D-type flip-flop 25 and an output terminal connected to the data input terminal of the D-type flip-flop 22; an OR gate 26 having a non-inverting output terminal Q of the D-type flip-flop 25 and the output terminal of an OR gate 28 connected to first and second input terminals, respectively; and a D-type flip-flop 27 having the output terminal of the OR gate 26 connected to its data input terminal and having the output clock of the VCO 206 input to its clock terminal. The D-type flip-flop 27 has an inverting output terminal QB connected to the second input terminal of the OR gate 21. The non-inverting output terminal Q of the D-type flip-flop 25 is input to the clock input terminal of the D-type flip-flop 29 and the inverting output terminal QB of the D-type flip-flop 29 is connected to its own data input terminal to thereby construct a frequency dividing circuit. The non-inverting output terminal Q of the D-type flip-flop 29 is input to the clock input terminal of the D-type flip-flop 30 and the inverting output terminal QB of the D-type flip-flop 30 is connected to its own data input terminal to thereby construct a frequency dividing circuit. The non-inverting output terminal Q of the D-type flip-flop 30 is output to the A counter 209 and B counter 210 as the frequency-divided output of the prescaler 207. The MC signal and the non-inverting output terminals Q of the D-type flip-flops 29 and 30 are input to the OR gate 28, the output of which is input to the OR gate 26.
Assume that the MC signal is at logic “1” (=HIGH). At such time the OR gate 28, one input of which is the MC signal, outputs logic “1”. The OR gates 26 outputs “1” at all times. In response to the output clock of the VCO 206, the D-type flip-flop 27 latches logic “1”, which is applied to its data input terminal, outputs logic “0” from its inverting output terminal QB and delivers this output to the OR gate 21.
The prescaler 207 is of the type that performs frequency division by 32 or 33. First, however, the 4-stage shift register comprising the D-type flip-flops 22, 23, 24, and 25 is driven by the output clock of the VCO 206 to perform frequency division by 8.
More specifically, the 4-stage shift register comprising the D-type flip-flops 22, 23, 24, and 25 composes a 4-bit ring counter driven by the output clock of the VCO 206. If the inverting output terminal QB of the D-type flip-flop 25 is “1”, the output of the OR gate 21 is “1”. One round is completed by eight clocks, which enter one at a time as the output clock from the VCO 206. The states of the D-type flip-flops 25, 24, 23, and 22 undergo a transition as follows: The state initially is “0000” and becomes “0001”, “0011”, “0111”“1111”, “1110”, “1100”, “1000”, and “0000” at the first, second, third, fourth, fifth, sixth, seventh and eighth clocks, respectively, of the output clocks from the VCO 206. The D-type flip-flop 25 alternatingly outputs four clocks of successive “1”s and four clocks of successive “0”s. Thus, the output of the D-type flip-flop 25 is a signal obtained by 1/8 division of the frequency of the output clock from the VCO 206.
The output of the D-type flip-flop 25 is input to the OR gate 26. The OR gate 26 inputs “1” to the data input terminal of the D-type flip-flop 27 and the inverting output terminal QB of the D-type flip-flop 27 is made “0”.
The non-inverting output terminals Q of the D-type flip-flops 29 and 30 enter the OR gate 28, the output of which is input to the data input terminal of the D-type flip-flop 27 via the OR gate 26.
The two stages of D-type flip-flops 29 and 30 compose a divide-by-4 frequency dividing circuit. The output of the 4-stage shift register comprising the D-type flip-flops 22, 23, 24 and 25 is divided by 4 by the D-type flip-flops 29 and 30. Thus, division by 32 is achieved.
When the MC signal is at logic “0” (=LOW), on the other hand, the OR gate 28 outputs logic “0” when the non-inverting output terminals Q of the D-type flip-flops 30 and 29 are both “0”. The OR gate 26 transmits the output at the non-inverting output terminal Q of D-type flip-flop 25 to the data input terminal D of the D-type flip-flop 27.
More specifically, the flip-flops 29 and 30 clocked by the 1/8 frequency-divided output of the 4-stage register comprising the D-type flip-flops 22, 23, 24 and 25 changes in state in the manner “1010”, and “1100”. The output of the OR gate 28 becomes “0” if the outputs of the flip-flops 29, 30 both become “0”, i.e., at a rate of once per four clocks output from the D-type flip-flop 25. When the output of the OR gate 28 is “0”, the D-type flip-flop 27 constructs a shift register together with the D-type flip-flops 22, 23, 24, and 25. At the moment the output of the OR gate 28 changes to “0”, the state of the D-type flip-flop 27 is “1” (because the output of OR gate 28 is “1” immediately prior thereto and “1” enters the data input terminal D of the D-type flip-flop 27 via the OR gate 26), the inverting output terminal QB of the D-type flip-flop 27 is “0”, the state of the D-type flip-flop 25 is “0” and the inverting output terminal QB of the D-type flip-flop 25 becomes “1”.
If the output of the OR gate 28 is “0”, the OR gate 26 transmits the output of the D-type flip-flop 25 to the data input terminal of the D-type flip-flop 27 as is. Whenever the output clock of the VCO 206 enters, the states of the D-type flip-flops 27, 25, 24, 23, and 22 undergo a transition in nine clock cycles in the following manner: “10000”, “00001”, “00011”, “00111”, “01111”, “11111”, “11110”, “11100”, “11000”, and “10000”.
That is, the shift register of prescaler 207 implements frequency division by 9. Among the four cycles of the divide-by-4 frequency dividing circuit of D-type flip-flops 29 and 30, division by 8 are executed in three cycles and division by 9 in one cycle.
Accordingly, when signal MC=“0” holds, the frequency-dividing factor of prescaler 207 is8×3+9=33
Described next will be a case where frequency division by N is carried out using a pulse-swallow-type variable frequency dividing circuit that employs the prescaler 207 and two programmable counters 209 and 210. Let N represents the total frequency-dividing factor. If a represents the quotient and b the remainder (where 0<b<32 holds) when N is divided by 32 (though a number other than 32 may be used, 32 is adopted here owing to the relationship to FIG. 15), then N will become as follows:N=32×a+b
In a case where N is obtained by frequency division by 32, 33, the above is transformed toN=32×(a−b)+33×b(where a>=b holds) and remainder b can be implemented by an operation dividing by 33 and dividing by 32 the remaining number of times. A pulse-swallow counter is implemented by the combination of two binary counters 209 and 210. In case of frequency division by 32, 33, a is the quotient obtained by dividing N by 32, e.g., a value of the six higher order bits or more, and b takes on the value of the five lower order bits. When an actual operation is performed, the A counter 209 and B counter 210 both count up to set count values A′, B′ or count down from the set values A′, B′ simultaneously in response to the output of the prescaler 207. In this case, the values A′, B′ become a, b, respectively.
Until the prescribed value b is attained or until the B counter 210 counts down to 0 starting from the count value b, the MC signal is placed at LOW level and the prescaler 207 performs division by 33. In other words, the B counter 210 counts the 1/33 frequency-divided output of the prescaler 207 b times. After the B counter 210 has counted the 1/33 frequency-divided output of the prescaler 207 b times, the MC signal is placed at HIGH level. The A counter 209 counts the 1/32 frequency-divided output of the prescaler 207 (a−b) times, namely the remaining number of times until the count value a is attained or until 0 is reached starting from a.
The frequency-dividing factor N, namelyN=32×(a−b)+33×bis realized by this series of operations. Thus it is possible to realize any frequency-dividing factor N.
With regard to publications relating to the above-described pulse-swallow-type variable frequency dividing circuit equipped with a prescaler having two frequency-dividing factors P and (P+1) and two counters, see the specifications of JP Patent Kokai Publication JP-A-6-69788 and JP-A-6-120815, by way of example.
In a case where the structure of the above-described pulse-swallow-type variable frequency dividing circuit is such that the output frequency of the VCO 206 is close to the boundary operating frequency of the device constituting the prescaler 207, adopting a hierarchical arrangement for the counters is a useful technique for obtaining any number of frequency divisions in an efficient manner.
However, since it is necessary to operate the shift register of the prescaler 207 by the output clock of the VCO 206, a large number of elements that operate at high speed are required.
Further, reducing power consumption is difficult because the A counter 209 and B counter 210 are operated simultaneously.
Furthermore, the MC signal supplied to the prescaler 207 is required to operate earlier than the output period of the prescaler 207, which performs a high-speed frequency dividing operation. This makes it difficult to design the proper timing.